// Copyright 2018 The Go Authors. All rights reserved.// Use of this source code is governed by a BSD-style// license that can be found in the LICENSE file.// Package cpu implements processor feature detection for// various CPU architectures.packagecpu// CacheLinePad is used to pad structs to avoid false sharing.typeCacheLinePadstruct{_[cacheLineSize]byte}// X86 contains the supported CPU features of the// current X86/AMD64 platform. If the current platform// is not X86/AMD64 then all feature flags are false.//// X86 is padded to avoid false sharing. Further the HasAVX// and HasAVX2 are only set if the OS supports XMM and YMM// registers in addition to the CPUID feature bit being set.varX86struct{_CacheLinePadHasAESbool// AES hardware implementation (AES NI)HasADXbool// Multi-precision add-carry instruction extensionsHasAVXbool// Advanced vector extensionHasAVX2bool// Advanced vector extension 2HasBMI1bool// Bit manipulation instruction set 1HasBMI2bool// Bit manipulation instruction set 2HasERMSbool// Enhanced REP for MOVSB and STOSBHasFMAbool// Fused-multiply-add instructionsHasOSXSAVEbool// OS supports XSAVE/XRESTOR for saving/restoring XMM registers.HasPCLMULQDQbool// PCLMULQDQ instruction - most often used for AES-GCMHasPOPCNTbool// Hamming weight instruction POPCNT.HasSSE2bool// Streaming SIMD extension 2 (always available on amd64)HasSSE3bool// Streaming SIMD extension 3HasSSSE3bool// Supplemental streaming SIMD extension 3HasSSE41bool// Streaming SIMD extension 4 and 4.1HasSSE42bool// Streaming SIMD extension 4 and 4.2_CacheLinePad}