Unverified Commit b29b2da1 authored by kladko's avatar kladko

SKALE-3596 Intel submission.

parent 845535ee
...@@ -115,7 +115,7 @@ void SGXWalletServer::printDB() { ...@@ -115,7 +115,7 @@ void SGXWalletServer::printDB() {
#ifdef SGX_HW_SIM #ifdef SGX_HW_SIM
#define NUM_THREADS 16 #define NUM_THREADS 16
#else #else
#define NUM_THREADS 64 #define NUM_THREADS 200
#endif #endif
......
...@@ -3,9 +3,9 @@ ...@@ -3,9 +3,9 @@
<ISVSVN>2</ISVSVN> <ISVSVN>2</ISVSVN>
<StackMaxSize>0x200000</StackMaxSize> <StackMaxSize>0x200000</StackMaxSize>
<HeapMaxSize>0x200000</HeapMaxSize> <HeapMaxSize>0x200000</HeapMaxSize>
<TCSNum>16</TCSNum> <TCSNum>256</TCSNum>
<TCSMaxNum>16</TCSMaxNum> <TCSMaxNum>256</TCSMaxNum>
<TCSMinPool>16</TCSMinPool> <TCSMinPool>256</TCSMinPool>
<TCSPolicy>0</TCSPolicy> <TCSPolicy>0</TCSPolicy>
<!-- Recommend changing 'DisableDebug' to 1 to make the enclave undebuggable for enclave release --> <!-- Recommend changing 'DisableDebug' to 1 to make the enclave undebuggable for enclave release -->
<DisableDebug>0</DisableDebug> <DisableDebug>0</DisableDebug>
......
...@@ -3,9 +3,9 @@ ...@@ -3,9 +3,9 @@
<ISVSVN>2</ISVSVN> <ISVSVN>2</ISVSVN>
<StackMaxSize>0x1000000</StackMaxSize> <StackMaxSize>0x1000000</StackMaxSize>
<HeapMaxSize>0x100000000</HeapMaxSize> <HeapMaxSize>0x100000000</HeapMaxSize>
<TCSNum>128</TCSNum> <TCSNum>256</TCSNum>
<TCSMaxNum>128</TCSMaxNum> <TCSMaxNum>256</TCSMaxNum>
<TCSMinPool>128</TCSMinPool> <TCSMinPool>256</TCSMinPool>
<TCSPolicy>0</TCSPolicy> <TCSPolicy>0</TCSPolicy>
<!-- Recommend changing 'DisableDebug' to 1 to make the enclave undebuggable for enclave release --> <!-- Recommend changing 'DisableDebug' to 1 to make the enclave undebuggable for enclave release -->
<DisableDebug>1</DisableDebug> <DisableDebug>1</DisableDebug>
......
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